1. Technical Field
This disclosure relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a self-aligned contact and a method of fabricating the same.
2. Description of the Related Art
A semiconductor device, such as a dynamic random access memory (DRAM), may include transistors, capacitors, load resistors, and interconnections. The interconnections include a contact plug that electrically connects conductive patterns. As semiconductor devices become highly integrated, the two-dimensional sizes of components are reduced and a plurality of layers may be required. Thus, the aspect ratio of the contact plug increases, and an alignment margin in a patterning process decreases, making it increasingly difficult to form the contact plug having a fine size in a desired position.
FIG. 1 is a cross-sectional diagram illustrating a method for forming a contact of a conventional semiconductor device.
Referring to FIG. 1, an isolation layer 13 is formed in a predetermined region of a semiconductor substrate 11. A lower conductive pattern 15 may be formed on the semiconductor substrate 11 having the isolation layer 13. A first interlayer dielectric layer 17 may be formed on the semiconductor substrate 11 having the lower conductive pattern 15. An upper conductive pattern 19 may be formed on the first interlayer dielectric layer 17. The upper conductive pattern 19 may partially overlap the lower conductive pattern 15. A second interlayer dielectric layer 21 and a third interlayer dielectric layer 23 may be sequentially formed on the semiconductor substrate 11 having the upper conductive pattern 19.
Thereafter, a first contact hole 26 and a second contact hole 27 are formed through the first, second, and third interlayer dielectric layers 17, 21, and 23 using a patterning process. The patterning process includes forming a mask pattern (not shown), such as a photoresist pattern, on the third interlayer dielectric layer 23 and sequentially and anisotropically etching the first, second, and third interlayer dielectric layers 17, 21, and 23 using the mask pattern as an etch mask. The first contact hole 26 sequentially penetrates the third and second interlayer dielectric layers 23 and 21 and partially exposes the upper conductive pattern 19. Also, the second contact hole 27 sequentially penetrates the third, second, and first interlayer dielectric layers 23, 21, and 17 and partially exposes the semiconductor substrate 11.
When the first interlayer dielectric layer 17 is anisotropically etched to form the second contact hole 27, the upper conductive pattern 19 functions as an etch stop layer. However, the patterning process has an alignment error. In other words, the alignment error causes the first and second contact holes 26 and 27 to be misaligned by an amount indicated by the arrow labeled “M.” In this case, the first contact hole 26 may deviate from the upper conductive pattern 19. Thus, while anisotropically etching the first interlayer dielectric layer 17 to form the second contact hole 27, an extended hole 26M may be formed at one side of the upper conductive pattern 19. The extended hole 26M exposes a sidewall of the upper conductive pattern 19 and also, partially exposes the lower conductive pattern 15 through the first interlayer dielectric layer 17.
Thereafter, a conductive layer (not shown) may be formed to fill the first and second contact holes 26 and 27. Here, the upper conductive pattern 19 should be electrically insulated from the lower conductive pattern 15 by the first interlayer dielectric layer 17. However, since the extended hole 26M is also filled with the conductive layer, the upper conductive pattern 19 is electrically connected to the lower conductive pattern 15 by the conductive layer. As a result, the extended hole 26M causes a contact failure.
Another method for forming interconnections of a semiconductor device is disclosed by U.S. Pat. No. 6,313,029 B1 to Kim entitled “Method for Forming Multi-layer Interconnection of a Semiconductor Device.” According to Kim, a method for forming a fine contact hole using a typical masking process is provided.
Embodiments of the invention address the above and other disadvantages of the conventional art.